提出了数模混合集成电路衬底耦合噪声的一种建模方案 :将集成电路芯片的衬底划分为多个 Voronoi图 ,计算各区域的 R、C值 ,在将衬底 RC网络映射到原电路网表之后 ,对新网表进行SPICE模拟 ,分析数模混合集成电路中的衬底噪声。用此模型模拟了两个数模混合集成电路的衬底耦合噪声 ,指出了在模拟电路关键器件周围加保护环是减少衬底耦合噪声的一种有效途径 A modeling scheme of substrate coupled noise of digital-analog hybrid integrated circuit is proposed. The substrate of integrated circuit chip is divided into several Voronoi diagrams, and the R and C values ​​of each region are calculated. After the substrate RC network is mapped to the original After the circuit netlist, SPICE simulation is carried out on the new netlist to analyze the substrate noise in the hybrid digital-analog integrated circuit. Using this model to simulate the substrate coupling noise of two digital-analog integrated circuits, it is pointed out that adding guard rings around the key components of analog circuits is an effective way to reduce the substrate coupling noise