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设计了一种全新的光路由器。采用单独的100 Mb/s的低速控制通道用来交换承载于波带(比特并行机制)带宽速率为80 Gb/s的包,这种基于现场可编程门阵列(FPGA)实现的机制使得宽带交换可以应用在具备低时延、低成本特点的本地网(LAN)中,商用化的FPGA用于驱动带宽的Mach-Zehnder干涉仪(MZI)和半导体光放大器(SOA)交换机。详细描述了为控制通道和数据通道设计的2种不同的时钟数据恢复模块(CDR)系统及其相关测试分析。对控制通道所有8个通道进行测试表明,在需要路由选址的情况下,测试结果稳定,且没有误码,和噪音层面出现。对于1 552.6 nm数据通道进行的背靠背和需要路由选址情况下,通过对MZI光交叉和SOA光交叉测量,得到额外的因为路由操作而导致的2.3 dB功率代价。
Designed a new optical router. A single 100 Mb / s low-speed control channel is used to exchange packets with a bandwidth of 80 Gb / s, which is carried in a band (bit-parallel) mechanism. This field-programmable gate array (FPGA) Applications In low latency, low cost local area networks (LANs), commercialized FPGAs are used for bandwidth-driven Mach-Zehnder interferometers (MZIs) and semiconductor optical amplifier (SOA) switches. Two different clock data recovery module (CDR) systems designed for control and data channels and their related test analysis are described in detail. Tests on all eight channels of the control channel show that the test results are stable with no bit errors and noise levels where routing is required. For back-to-back and route-needed locations for the 1 552.6 nm data path, additional 2.3 dB power penalty due to routing operations is obtained through MZI optical cross-over and SOA cross-measurement.