当对a-Si∶H TFT施加较大的漏-栅电压时,其泄漏电流主要取决于空穴在漏端耗尽区内的产生过程以及被有源层内中立陷阱捕获的过程。基于价带空穴和被陷阱所捕获空穴的一维连续性方程,推导出空穴在有源层内纵向传导的逃逸率。通过描述漏端耗尽区内空穴的产生率以及在a-Si∶H层内空穴传导的逃逸率,建立了a-Si∶H TFT的泄漏电流模型,并进行了相应验证。 When a large drain-to-gate voltage is applied to the a-Si: H TFT, the leakage current mainly depends on the generation of holes in the drain depletion region and the capture by neutral traps in the active layer. Based on the one-dimensional continuity equation of valence band holes and cavities captured by traps, the escape rate of holes conducting longitudinally in the active layer is deduced. The leakage current model of a-Si: H TFT was established by describing the generation rate of holes in the depletion region and the escape rate of hole conduction in the a-Si:H layer, and the corresponding verification was carried out.