设计了一种用于流水线型A/D转换器的10位160 MS/s CMOS采样保持器。电路采用电容翻转式结构,以及运用增益提高技术(gain-boosting)的折叠式共源共栅放大器,以满足高速、高精度的要求;优化采样电容和运算放大器指标,以保证噪声容限和线性指标;优化辅助运放,从而保证运放的稳定性。HSPICE仿真结果表明,在78.83 MHz输入信号、160.34 MHz工作频率下,输出信号的无杂散动态范围为77.3 dB。 A 10-bit, 160 MS / s CMOS Sample-and-Hold for Pipelined A / D Converter is designed. The circuit uses a capacitive flip-up structure and a folded cascode amplifier using gain-boosting to meet high-speed and high-precision requirements. The sampling capacitors and op amp specifications are optimized to ensure noise margin and linearity Indicators; optimize the auxiliary op amp, thus ensuring the stability of op amp. HSPICE simulation results show that the spurious-free dynamic range of the output signal is 77.3 dB at an operating frequency of 160.34 MHz for the 78.83 MHz input signal.