论文部分内容阅读
描述一个基于0.6μm CM O S工艺的、低功耗的13 b,107样品/s流水线模数转换器(ADC)的设计。为了达到13 b的转换精度,在电路设计中采用了电容误差平均技术;为了实现低功耗设计,在电路设计中综合采用了运算放大器共享、输入采样保持放大器消去、按比例缩小和动态比较器等技术。在考虑工艺实现中的非理想因素的条件下,对ADC电路进行晶体管级M on te-C arlo仿真,当ADC以10MH z的采样率对1MH z的正弦输入信号进行采样转换时,在其输出得到了82 dB的非杂散动态范围,并且此时ADC模拟部分的功耗仅为11mW。
Describe the design of a low power 13 b, 107 sample / s pipelined analog-to-digital converter (ADC) based on a 0.6 μm CM O S process. In order to achieve the 13 b conversion accuracy, the circuit design uses a capacitor error averaging technique; in order to achieve low-power design, integrated circuit design op amp sharing, input sample and hold amplifier to eliminate, downscaling and dynamic comparator And other technologies. Considering the non-ideal factors in the process of implementation, the ADC circuit transistor-level M on te-C arlo simulation, when the ADC to 10MH z sampling rate of 1MH z sinusoidal input signal sampling conversion, the output Got 82 dB of non-spurious dynamic range, and ADC analog part of the power consumption is only 11mW.