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提出并演示了一新型的低成本亚 5 0纳米多晶硅栅制作技术 .该技术的特点是它与光刻分辨率无关 ,即不需要高分辨率光刻技术 .纳米尺度的栅掩膜图案是由台阶侧壁图形的转移所形成 .实验结果表明 ,该技术制成的硅栅的栅长由形成侧壁图形的薄膜之厚度所决定 ,大致为该厚度的 75 %— 85 % .SEM照片显示硅栅的剖面为倒梯形结构 .与其它结构 (如矩形或正梯形 )相比 ,该结构有利于减少栅电阻 .
A new low-cost sub-50nm polycrystalline silicon gate fabrication technology is proposed and demonstrated, which is characterized by its independence from the resolution of lithography, ie, the high-resolution lithography technology is not required. The nano-scale gate mask pattern is composed of The results of the experiments show that the gate length of the silicon gate made by this technique is determined by the thickness of the thin film forming the sidewall pattern, which is approximately 75% -85% of the thickness. The SEM picture shows the silicon The cross section of the gate is an inverted trapezoidal structure, which is advantageous for reducing the gate resistance compared to other structures such as rectangular or regular trapezoid.