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为了解决数字锁相频率合成中频率分辨率与环路带宽之间的矛盾,我们提出了一种新型的数字频率合成锁相环的设计方案。由参考文献可知,这种新型锁相环之所以能够解决上述矛盾,关键在于环路分频参数控制器能够根据所需产生的输出频率f_0,按照一定的规则和算法设置一组分频参数N 及N_i,从而使环路鉴相器输出谐波的频率(即鉴相器输出端干扰的频率)独立于环路频率分辨率△f_0。因此,对新型环路鉴相器输出电压进行详细的频谱分析是十分必要的;同时,为了使环路分频参数控制器根据所需产生的输出频率f_0,按照参考文献中的算法求得分频参数N 及N_i,首先求出算法中参数A_0和A_i 的值是至关重要的。
In order to solve the conflict between frequency resolution and loop bandwidth in digital PLL, we propose a new design scheme of PLL for digital frequency synthesis. From the reference, we know that the reason why the new phase-locked loop can solve the above contradiction, the key is that the loop frequency divider parameters controller based on the required output frequency f_0, in accordance with certain rules and algorithms to set a set of frequency-dividing parameters N And N_i, so that the loop phase detector output harmonic frequency (ie phase detector output frequency interference) independent of the loop frequency resolution △ f_0. Therefore, a detailed analysis of the output voltage of the new loop phase detector is necessary. In the meantime, in order to make the loop frequency division controller to calculate the output frequency f_0 according to the required algorithm according to the reference Frequency parameters N and N_i, the first algorithm to calculate the parameters A_0 and A_i value is crucial.