This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register(SAR)analog-to-digital converter(ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed,a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay,and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 200 m2is occupied. This paper demonstrates a single-channel 10-bit 160 MS / s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is reduced to accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is applied in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of ​​250 200 m2is occupied.