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介绍了视频压缩国际标准MPEG2(MovingPicturesExpertGroup)中有关逆量化的算法,设计了一种适用于MPEG2视频解码的逆量化器VLSI结构,并用VHDL语言进行了仿真。采用改进的高速Booth流水线乘法器提高电路速度。用1μmCMOS单元库进行综合,在50MHz时钟频率下,电路规模为3000门左右。关键路径延时为17ns,该电路可应用于MPEG2视频解码器。
The algorithm of inverse quantization in Moving Picture Experts Group (MPEG2) is introduced. An inverse quantizer (VLSI) structure suitable for MPEG2 video decoding is designed and simulated in VHDL language. Improved circuit speed with improved high-speed Booth pipeline multipliers. With 1μmCMOS cell library synthesis, the clock frequency of 50MHz, the circuit size of about 3000. The key path delay is 17ns, this circuit can be applied to MPEG2 video decoder.