针对传统的四相移键控(QPSK)的调制解调方式。提出一种基于高速硬件描述语言(VHDL)的数字式QPSK调制解调模型。这种新建模方式便于在目标芯片FPGA/CPLD上实现QPSK调制解调功能。新的QPSK调制器根据其调制模型,采用分频器和选择开关来实现;新的QPSK解调器模型引入一个特殊相位计数模块,对已调信号进行解调。通过理论推导和系统VHDL的编程设计与时序仿真,结果表明新型QPSK调制解调器模型在理论和实用上是可行的,并且此种设计方案减小了硬件实现的复杂度,具有可移植性好、体积小、低功耗、可靠性高、方便维护和升级等优点。 The traditional quadrature phase shift keying (QPSK) modulation and demodulation methods. A digital QPSK modulation and demodulation model based on high-speed hardware description language (VHDL) is proposed. This new modeling approach facilitates QPSK modulation and demodulation on the target FPGA / CPLD. The new QPSK modulator is implemented using a divider and selector switch based on its modulation model; the new QPSK demodulator model introduces a special phase counter module that demodulates the modulated signal. The theoretical derivation and VHDL programming design and timing simulation show that the new QPSK modem model is feasible theoretically and practically, and this design scheme reduces the complexity of hardware implementation and has the advantages of good portability, small size , Low power consumption, high reliability, easy maintenance and upgrades.