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本文以上海楷登电子科技有限公司(Cadence)的时序分析工具(Tempus)为例,浅析集成电路设计行业对信号延迟的分析和处理方法。主要包含两部分:第一部分是对基本信号延迟(Basic Delay)的浅析,包括传统方法的信号延迟的计算方法和现阶段业界广泛应用的等价波形模型的计算方法。第二部分是对噪声引起的增量信号延迟(Incremental Dealy)的浅析,解释了增量信号延迟的影响,以及常用的解决方案。
In this paper, Cadence timing analyzer (Shanghai Cadence) as an example to analyze the integrated circuit design industry, the signal delay analysis and processing methods. There are mainly two parts: The first part is the basic signal delay (Basic Delay) analysis, including the traditional method of signal delay calculation method and the current industry widely used equivalent waveform model calculation method. The second part is an analysis of noise-induced incremental signal delay (Incremental Dealy), explaining the effect of incremental signal delay and commonly used solutions.