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比较器在模数转换及其他模拟功能模块中都是非常重要的器件,其速度和精度直接影响模块的功能。采用SMIC 0.18 CMOS混合信号工艺,设计了一种轨到轨电压比较器,电路结构主要包括前置放大器、锁存器和输出缓冲电路,此外,采用一种β倍增的自偏置基准电路提供偏置电流。结果表明,在3.3 V的供电电压下,提供共模范围为300 m V~3.3 V的信号,可分辨输入信号的最小频率为200 MHz,单级运放相位裕度大于60°,输出信号占空比为40%~60%,比较阈值约为10 m V,输入输出延时小于5 ns,功耗小于18 m W,版图面积小于200μm×150μm。该比较器的失真较小,在整个输入信号范围内有较高的共模抑制比,较大限度地提高了电路的性能。
Comparators are very important components in analog-to-digital conversion and other analog functional blocks whose speed and accuracy directly affect the functionality of the block. Using SMIC 0.18 CMOS mixed-signal technology, a rail-to-rail voltage comparator is designed. The circuit structure mainly includes preamplifier, latch and output buffer circuit. In addition, a β multiplication self-bias reference circuit is used to provide partial Set the current. The results show that at a supply voltage of 3.3 V, a signal with a common-mode range of 300 mV ~ 3.3 V is provided. The minimum frequency of the distinguishable input signal is 200 MHz and the phase margin of a single-stage operational amplifier is greater than 60 °. The output signals The space ratio is 40% -60%. The comparison threshold is about 10 mV. The input / output delay is less than 5 ns. The power dissipation is less than 18 mW. The layout area is less than 200μm × 150μm. The comparator has low distortion and high common-mode rejection over the entire input signal range, greatly improving the performance of the circuit.