数字下变频(DDC)是软件无线电系统的关键技术之一,可将高频数据流信号变成低频数据流信号,以适宜于后端数字信号处理器设备实时处理。分析了下变频器的各个组成模块:数字振荡控制器(NCO)、级联积分梳妆(CIC)滤波器、有限长单位冲激响应(FIR)滤波器。并在此基础上对各个模块提出改进方式,给出了一种改进型基于FPGA的数字下变频的设计方案,实验结果表明,改进型数字下变频技术可减少对FPGA内部逻辑资源的消耗,具有可用性和实用性。 Digital Down Converter (DDC) is one of the key technologies in software radio systems. It can convert high-frequency data stream signals into low-frequency data stream signals and is suitable for real-time processing of back-end digital signal processor devices. The components of the downconverter are analyzed, including NCO, CIC and FIR filters. Based on this, an improved method for each module is proposed. An improved digital downconversion design scheme based on FPGA is given. The experimental results show that the improved digital downconversion technology can reduce the consumption of logic resources in the FPGA. Usability and practicality.