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本文提出一种改进型萧脱基晶体管逻辑电路的结构,称为MSTL。它具有标准STL高速度的优点,又具有ISL只需要一种萧脱基二极管的简化工艺优点,而且集成度稍高于STL和ISL。它的逻辑摆幅由萧脱基二极管正向压降决定,采用铝硅萧脱基二极管,电路的逻辑摆幅为400mv。实验中,选用氧化隔离技术,多晶硅发射极晶体管和铝硅萧脱基二极管做在N/N~+/P~+外延片上构成MSTL。结果表明,用4μm的设计规范,在50μA的工作电流下,获得3.5ns的传输延迟时间。
This paper presents an improved structure of the Hedy transistor logic circuit, known as MSTL. It has the benefits of standard STL speed and ISL’s simplified process advantages that only require a Schottky diode, with slightly higher integration than STL and ISL. Its logic swing is determined by the forward voltage drop of the Schottky diode. The silicon schottky diode is used. The logic swing of the circuit is 400mv. In the experiment, the oxide isolation technology, polysilicon emitter transistor and silicon aluminum oxide diode are used to form MSTL on N / N ~ + / P ~ + epitaxial wafers. The results show that with a 4 μm design specification, a transfer delay of 3.5 ns is achieved at a 50 μA operating current.