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我们开发了一种新型可配置逻辑阵列测试结构,它采用高度可伸缩且兼具功耗低和配置时间短两大优势的第3代分离栅极闪存单元。此分离栅极Super Flash配置元件(SCE)已通过90nm嵌入式闪存技术进行了演示。得到的SCE消除了对深奥的制造工艺、检测和SRAM电路的需求,并缩短了可编程阵列(PA)(例如,FPGA和CPLD)的配置时间。此外,SCE本身还具有SST分离栅极闪存技术的优点,包括紧凑的区域、低电压读操作、低功耗多晶硅间(pol y-t o-pol y)擦除、源极侧通道热电子(SSCHE)注入编程机制以及超高的可靠性。
We have developed a new configurable logic array test architecture that uses a third-generation split gate flash memory cell that is highly scalable and offers two advantages of low power consumption and short configuration time. This split-gate Super Flash ™ Configuration Element (SCE) is demonstrated with 90nm embedded flash technology. The resulting SCE eliminates the need for esoteric manufacturing process, detection, and SRAM circuitry and reduces the configuration time of programmable arrays (such as FPGAs and CPLDs). In addition, the SCE itself offers the benefits of SST’s split-gate flash technology, including compact area, low-voltage read operation, low-power pol y erase, source side channel hot electron (SSCHE) Injection programming mechanism and high reliability.