Based on the coordinate rotation digital computer (CORDIC) algorithm, the high-speed kinematics calculation for a six degree of freedom (DOF) space manipulator is implemented in a field programmable gate array (FPGA) co-processor. A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation. The CORDIC soft-core and the CORDIC-based pipelined kinematics calculation co-processor are described with the very-high-speed integrated circuit hardware description language (VHDL) language and realized in the FPGA. Finally, the feasibility of the design is validated in the Spartan-3 FPGA of Xilinx Inc., and the performance specifications of FPGA co-processor are discussed. The results show that time-consumption of the kinematics calculation is greatly reduced.