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Virtuoso~AMS Designer(AMSD)包含大量尖端功能,超越了SpectreVerilog等其他解决方案。尽管如此,很多客户仍然使用SpectreVerilog,因为从SpectreVerilog移植到AMSD存在很多障碍和易用性问题。本文将会讨论在PDK转化、设计调整和Verilog文本用法等中间会遇到的障碍以及解决方案。此外,本文还会讨论具体的性能改进以及可用性和可调试性的改进。AMSD流程中加入了新的网表分析器(OSS网表分析器),以及一种新的仿真器流程,使得这些解决方案成为可能。此外AMSD仿真器本身也有很多重大性能改进。本文的最后部分将会详细介绍简单易行的移植过程,并且将会对照SpectreVerilog讨论具体的性能改进。这种新的方法学让客户可以用最低的代价迅速移植到AMSD并享受其丰富的语言支持和功能,从而大大提高设计工程师的生产效率。根据本文中所提到的解决方案,SpectreVerilog移植到AMSD的过程可以从一个月缩短至不到一天。设计工程师的效率也因为可用性、可调试性和性能的提升而得到进一步提升。这些都将在本文中提到,并附带性能的对比。
Virtuoso ~ AMS Designer (AMSD) includes a number of cutting-edge features that go beyond other solutions such as SpectreVerilog. Nonetheless, many customers still use SpectreVerilog because of the many handicap and ease of use issues associated with migrating from SpectreVerilog to AMSD. This article discusses the hurdles and solutions that come with PDK conversion, design changes, and Verilog text usage. In addition, this article also discusses specific performance improvements and improvements in usability and debugability. These solutions are made possible by the addition of a new Netlist Analyzer (OSS Netlist Analyzer) to the AMSD process and a new emulator process. In addition AMSD emulator itself also has a lot of major performance improvements. The final part of this article will detail the easy migration process and will discuss specific performance improvements against SpecterVerilog. This new methodology allows customers to quickly migrate to AMSD with minimal language costs and enjoy their rich language support and functionality, greatly improving design engineer productivity. Based on the solution presented in this article, the migration of SpecterVerilog to AMSD can be shortened from one month to less than a day. The efficiency of a design engineer is further enhanced by availability, debugability, and performance improvements. These are mentioned in this article, and with the performance comparison.