业界第一个1.8V在系统可编程(ISP)复杂可编程逻辑器件(CPLD)系列ispMACH4000日前由Lattice公司推出。这一系列器件是Lattice第三代BFW产品。由于首次采用了0.18微米的CMOS工艺,因此该系列产品的功耗较常规2.5V的CPLD产品下降了70～90％,其引脚至引脚的时延(tPD)、时钟至输出的迟延(tCO),信号建立时间和工作频率(rFMAX)比 The industry’s first 1.8V is now available from Lattice in the ISP family of programmable logic device (CPLD) ispMACH4000s. This series of devices is the third generation of Lattice BFW products. The 0.18-μm CMOS technology is the first to consume 70 to 90 percent less power than conventional 2.5-V CPLDs, with pin-to-pin delay (tPD) and clock-to-output delay tCO), signal settling time and operating frequency (rFMAX) ratio