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通过分析AES算法的基本原理,对AES算法中的子模块SubBytes和Mixcolumns的硬件电路实现方法进行优化,提出一种新的key硬件电路实现方式,并在key的实现电路中采用低功耗设计。与目前的大多数实现电路相比,该电路可以有效减小芯片面积,降低电路功耗。采用串行AES加密/解密电路结构,经综合仿真后,芯片面积为8 054门,最高工作频率为77.4 MHz,对128位数据加密的速率为225 Mbps,解密速率达到183 Mbps,可满足目前大部分无线传感网络数据交换速率的需求。
By analyzing the basic principle of AES algorithm, the sub-modules SubBytes and Mixcolumns in the AES algorithm are optimized, and a new hardware implementation of the key hardware is proposed. A low-power design is adopted in the key implementation circuit. Compared with most current implementation circuits, the circuit can effectively reduce the chip area and reduce the circuit power consumption. The serial AES encryption / decryption circuit structure, integrated simulation, the chip area of 8 054, the maximum operating frequency of 77.4 MHz, 128-bit data encryption rate of 225 Mbps, decryption rate of 183 Mbps, to meet the current large Part of the wireless sensor network data exchange rate needs.