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为解决集成电路的全芯片静电防护设计中寄生电阻导致的防护空间压缩问题,提出了一种实用的能够在版图设计过程中提高集成电路静电放电(ESD)防护能力的仿真方法,用于评估和控制ESD电流通路上的寄生电阻,辅助ESD防护设计,预估器件静电防护等级。详细介绍了仿真方法的原理和流程,以0.18μm SOI CMOS工艺制造的静态随机存储器电路为仿真和实验对象,应用此仿真方法,统计寄生电阻值,优化ESD防护设计,并进行ESD测试,记录未优化样品和优化样品的失效电压。通过对比寄生电阻和失效电压,证明降低寄生电阻可获得更好的ESD防护性能,而且器件失效电压和关键寄生电阻值R Vdd之间存在近似线性反比关系。
In order to solve the problem of compressing the protection space caused by the parasitic resistance in the IC full-chip ESD protection design, a practical simulation method to improve the ESD protection capability of the integrated circuit during the layout design is proposed to evaluate and Control the parasitic resistance on the ESD current path, assist ESD protection design, and predict the ESD protection level of the device. The principle and flow of the simulation method are introduced in detail. The static random access memory (SRAM) circuit fabricated in 0.18μm SOI CMOS process is used as the simulation and experimental object. By using this simulation method, the parasitic resistance is calculated, ESD protection is optimized, and ESD test is performed. Optimize samples and optimize samples for failure voltage. By comparing the parasitic resistance and the failure voltage, it is demonstrated that lowering the parasitic resistance leads to better ESD protection performance and there is an approximately linear inverse relationship between the device failure voltage and the critical parasitic resistance value, R Vdd.