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为了进一步优化高压LDMOS器件的耐压和比导通电阻的关系,提出了一种新颖的隔离式双n型深阱高压n型沟道LDMOS器件结构。采用独特的双n型深阱结构工艺替代传统结构工艺中的单n型深阱,解决了垂直方向上的pnp(p型阱-DNW-p型衬底)穿通问题和横向漏端扩展区的耐压与比导通电阻的优化问题的矛盾。器件仿真和硅晶圆测试数据显示,在0.35μm的工艺平台上,采用新结构的器件在满足100 V的耐压下,比导通电阻达到122 mΩ·mm2。同时,非埋层工艺使成本大幅下降。
In order to further optimize the relationship between breakdown voltage and on-resistance of high-voltage LDMOS devices, a novel isolated n-type deep well n-channel n-channel LDMOS device structure is proposed. A unique double n-type deep well structure process is adopted to replace the single n type deep well in the conventional structure process to solve the problem that the pnp (p-type well-DNW-p substrate) punch-through problem in the vertical direction and the lateral drain extension area Conflict between voltage and on-resistance optimization. Device simulation and silicon wafer test data show that in the 0.35μm process platform, the new structure of the device to meet the 100 V withstand voltage, the specific resistance of 122 mΩ · mm2. At the same time, non-buried processes have led to a significant cost reduction.