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通过对时态逻辑的研究来探讨时态逻辑在硬件设计形式化验证上的应用 ,同时对布尔函数在计算机内的表示二叉判定图 (BDD)进行了进一步地分析 ,最后给出了一个时态逻辑对硬件设计进行验证的例子
Through the study of temporal logic, the application of temporal logic in the formal verification of hardware design is discussed. At the same time, the BDD of the Boolean function in computer is further analyzed. Finally, State logic to verify the hardware design examples