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为了满足在一个系统中使用多码率低密度奇偶校验(LDPC)码字的需求,设计了一个多码率准循环LDPC(QC-LDPC)码编码器;按照功能,将编码器分成输入缓存单元(ISU)、生成矩阵存储单元(GMSU)、矩阵乘法运算单元(MMU)以及输出缓存单元(OSU)4个主要组成部分;通过使用多个小块存储器组合的方式设计ISU可以使无效存储空间降到最低;通过分析各种码率生成矩阵特点,将矩阵进行分割,从而将各种码率生成矩阵所需要的信息存储在若干个存储单元中;MMU用于完成信息位与矩阵的乘法与求和运算,运算单元的数目和GMSU的数目相等;OSU中包括两个存储器,采用乒乓操作,以提高编码速率。通过管脚的选择,此编码器支持0.4,0.6以及0.8码率3种编码模式。最后用Altera公司的现场可编程门阵列(FPGA)EP1S801508C7对编码器进行了实现。结果显示此编码器仅耗费5339个逻辑单元,占FPGA总逻辑单元的7,耗费439296比特的存储器资源,占FPGA总存储器资源的6%。
In order to meet the requirement of using multi-rate low-density parity check (LDPC) code words in one system, a multi-rate quasi-cyclic LDPC (QC-LDPC) coder is designed. According to the function, the encoder is divided into an input buffer ISU, GMSU, MMU, and OSU. By designing the ISU by using a combination of a plurality of small blocks of memory, invalid storage space To a minimum. By analyzing the characteristics of various rate-generating matrices, the matrix is segmented to store the information needed by various rate-generating matrices in a number of memory locations. The MMU is used to perform the multiplication and multiplication of information bits and matrices Summation, the number of computing units and the number of GMSU equal; OSU includes two memories, using ping-pong operation, in order to improve the encoding rate. Through the choice of the pin, this encoder supports 0.4, 0.6 and 0.8 code rate 3 encoding modes. Finally, using Altera’s field programmable gate array (FPGA) EP1S801508C7 on the encoder. The results show that this encoder only consumes 5339 logic cells, accounting for 7 of the FPGA’s total logic cells, consuming 439,296 bits of memory resources, accounting for 6% of the total FPGA memory resources.