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给出了一种适用于数字接收机的位同步数字锁相环算法。首先分析了数字锁相环的各个组成部分,详细推导了数字锁相环路中环路滤波器参数、鉴相增益等各个参数的计算公式;然后利用Matlab分别仿真了环路对输入信号相位和频率阶跃的响应,对仿真结果进行了分析。仿真结果表明,采用数字锁相环的位同步电路对输入信号的相位和频率阶跃具有较好的跟踪性能。最后说明了在环路设计中应该注意的几个问题。
A bit synchronization digital phase locked loop algorithm suitable for digital receiver is given. Firstly, the various components of the digital phase-locked loop are analyzed, and the formulas for calculating the parameters of the loop filter, such as the phase-locked loop filter in the digital phase-locked loop are deduced in detail. Then, the phase and frequency of the input signal Step response, the simulation results were analyzed. The simulation results show that the digital phase-locked loop bit synchronization circuit has good tracking performance on the phase and frequency steps of the input signal. Finally, some problems should be noticed in the loop design.