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由于空间成像套刻(Overlay)技术的预算随集成电路(IC)设计规范的紧缩而吃紧,因此,Overlay测量技术准确度的重要意义也随之提高。通过对后开发(AfterDevelopDI)阶段和后蚀刻(AfterEtchFI)阶段的Overlay测量结果进行比较,研究了0.18μm设计规范下的铜金属双重镶嵌工艺过程中的Overlay准确度。在确保对同一个晶圆进行后开发(DI)阶段和后蚀刻(FI)阶段测试的条件下,我们对成品晶圆的5个工艺层进行了比较。此外,还利用CD-SEM(线宽-扫描电子显微镜)测量了某个工艺层(PolyGate)上的芯片内Overlay,并与采用分割线方法的光学Overlay测量结果进行了比较。发现对芯片内overlay的校准存在着严重的局限性,即在应用CD-SEM时缺乏合适的结构进行Overlay测量。我们还将继续为大家提供定量的比较结果,同时也会向大家推荐组合的CD-SEM测量结构,使其能够被应用到今后的光刻设计中。
As the budget for space imaging overlays is tightened with IC design constraints, the significance of Overlay measurement accuracy increases. By comparing the Overlay measurements in the AfterDevelopDI and AfterEtchFI stages, the Overlay accuracy in the CuMD damascene process with the 0.18μm design rule was studied. The five process layers of the finished wafer were compared to ensure that the same wafer was tested for the post-development (DI) and post-etch (FI) phases. In addition, on-chip Overlay was measured on a PolyGate using CD-SEM (Linewidth-Scanning Electron Microscopy) and compared with optical Overlay measurements using the split-line method. It has been found that there is a serious limitation in the calibration of the overlay in the chip. That is, there is a lack of appropriate structure for Overlay measurement when applying CD-SEM. We will also continue to provide quantitative comparison results for everyone, and we will also recommend a combination of CD-SEM measurement structure, so that it can be applied to future lithography design.