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微电子学线路的复杂性正在迅速增长,这使集成电路的设计者和制造者面临着一些新的技术上的困难。到八十年代末,在单个集成电路块上堆积上百万个逻辑门电路也许同样是可能的。但是,无缺陷集成块的产率会随着组件数的越来越大而急剧下降。用现行的平版印刷技术少量生产定制线路常常是不经济的,因而人们普遍感到半导体工业不能满足对这样线路的需要。此外,这些平版印刷程序不能生产大于几平方英寸的大面积集成电路,而且它们周转时间缓慢,从而阻碍人们进行越来越微型化
The complexity of microelectronics circuits is rapidly increasing, which presents some new technical difficulties for designers and manufacturers of integrated circuits. By the late 1980s, it might also be possible to stack millions of logic gates on a single integrated circuit block. However, the yield of defect-free blocks drops dramatically with the number of components. It is often uneconomical to produce custom lines in small quantities using current lithographic techniques, and it is generally felt that the semiconductor industry can not meet the needs for such lines. In addition, these lithography processes can not produce large area integrated circuits greater than a few square inches, and their turnaround time slows down the miniaturization of people