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基于CMV2000高速大面阵探测器构建了图像处理系统,为了在100 fps帧率的情况下同时采集和处理2片2 K×1 K面阵的图像,系统必须拥有足够的带宽缓存数据。采用Xilinx公司Virtex5系列FPGA作为主控器件,4片数据速率为533 Mbit/s的DDR2 SDRAM作为缓存设备,实现数据的采集、缓存和处理。高速并行的DDR2 SDRAM数据线的信号完整性将成为系统设计的薄弱环节,因此在电路硬件实际投入制造之前进行仿真是十分必要的。采用Cadence公司的Sig Xplore和Sig Noise仿真工具对系统中DDR2 SDRAM的数据线进行了反射和串扰的仿真,得出了使用片上终端匹配(ODT)和数控阻抗(DCI)技术进行阻抗匹配时数据线的反射引起的信号上冲和下冲都在器件要求的范围之内,数据线在8 mil线宽8 mil间距2 000 mil耦合距离的情况下串扰噪声在信号的噪声容限之内等结论。研究了高带宽的高速大面阵图像系统信号完整性仿真方法,仿真结果能够满足系统要求,从而为解决此类问题提供了思路和途径。
Based on the CMV2000 high-speed large-area array detector, an image processing system is constructed. In order to capture and process two 2K × 1K area images simultaneously at a frame rate of 100 fps, the system must have enough bandwidth cached data. Using Xilinx Virtex5 series FPGA as the master device, four data rates of 533 Mbit / s DDR2 SDRAM as a cache device for data acquisition, caching and processing. The signal integrity of high-speed parallel DDR2 SDRAM data lines will be a weak point in system design, so it is imperative to simulate the circuit hardware prior to actually putting it into production. Using Cadence’s Sig Xplore and Sig Noise simulation tools, the data lines of DDR2 SDRAM in the system were simulated with reflection and crosstalk. The data lines obtained using on-chip termination matching (ODT) and digital impedance (DCI) Of the signal caused by the reflection and undershoot of the signal are within the scope of the device requirements, the data line in the 8 mil line width 8 mil spacing 2 000 mil coupling distance crosstalk noise within the signal noise margin and so on. The signal integrity simulation method of high-speed large area array image system with high bandwidth is studied. The simulation results can meet the system requirements and provide ideas and ways to solve such problems.