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设计了一个锁相环频率合成芯片。该芯片集晶体振荡电路、鉴频鉴相器、电荷泵、分频器、低通环路滤波器和压控振荡器(VCO)等电路于一体。详细分析了频率综合器中的各个关键模块,利用MATLAB软件优化环路参数,简化了电荷泵、VCO和片内环路参数的相关设计。最后,给出了芯片照片和流片测试结果,验证了设计方法和电路设计的正确性。该芯片在0.35μm CMOS工艺下进行了流片,测试结果表明,电源电压3 V,电流25 mA,芯片面积为5.4 mm2(3 000μm×1 800μm)。输出频率0.8~1.2 GHz,步进50 MHz,单边带相位噪声优于-106 dBc/Hz@1 kHz,-106 dBc/Hz@10 kHz,-115 dBc/Hz@100 kHz,-124 dBc/Hz@1MHz,-140 dBc/Hz@10 MHz。
Design a PLL frequency synthesis chip. The chip set crystal oscillator circuit, phase frequency detector, charge pump, divider, low-pass loop filter and voltage-controlled oscillator (VCO) and other circuits in one. The key modules in the frequency synthesizer are analyzed in detail. The MATLAB software is used to optimize the loop parameters to simplify the design of the charge pump, VCO and on-chip loop parameters. Finally, chip photos and tape test results are given, verifying the correctness of the design method and circuit design. The chip was run on a 0.35μm CMOS process. The test results show that the power supply voltage is 3 V, the current is 25 mA, and the chip area is 5.4 mm2 (3 000 μm × 1 800 μm). The output frequency is 0.8 to 1.2 GHz with 50 MHz steps with single sideband phase noise better than -106 dBc / Hz @ 1 kHz, -106 dBc / Hz @ 10 kHz, -115 dBc / Hz @ 100 kHz, -124 dBc / Hz @ 1MHz, -140 dBc / Hz @ 10 MHz.