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采用0.18μm CMOS六层金属工艺,利用带中心抽头的对称螺旋电感和新型电容调谐阵列构成的LC谐振回路,设计并实现了一种低功耗低相位噪声的数字控制振荡器(DCO)。流片测试结果表明,相位噪声在1MHz偏移频率处为-119.77dBc/Hz。电路采用1.8V电源供电,消耗约4.9mA电流,当电源电压降到1.6V时,消耗约4.1mA的核心电路电流,此时,相位噪声在1MHz频偏处仍达到-119.1dBc/Hz。为了提高全数字锁相环设计效率,采用硬件描述语言,构建了一种适用于全数字锁相环的仿真模型。该模型能大大缩短早期系统级架构选择和算法级行为验证的时间。
A 0.18μm CMOS six-layer metal process is used to design and implement a DCO with low power consumption and low phase noise by using a center-tapped symmetric spiral inductor and a novel LC resonant circuit with a capacitor tuning array. The flow test results show that the phase noise is -119.77 dBc / Hz at a 1 MHz offset frequency. The circuit operates from a 1.8V supply and consumes approximately 4.9mA. When the supply voltage drops to 1.6V, it consumes about 4.1mA of core circuit current. At this point, the phase noise still reaches -119.1dBc / Hz at 1MHz offset. In order to improve the design efficiency of all-digital phase-locked loop, a hardware description language is adopted to construct a simulation model suitable for all-digital phase-locked loop. This model greatly reduces the time required for early system level architecture selection and algorithmic level behavior verification.