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为了提高CAVLC解码器的解码速率,提出了一种优化的CAVLC解码器结构,主要包括level解码模块和RunBefore解码模块。level解码模块采用伪并行的结构解码幅值,实现了半个周期解码一个幅值;采用RunBefore与level快速合并的方法,在RunBefore解码完成的同时形成残差系数。建立了该优化结构的RTL模型,并验证了其功能的正确性。利用Xilinx公司的ISE13.3对该设计进行综合,结果显示该设计可以支持1 080p高清视频的实时解码。
In order to improve the decoding rate of CAVLC decoder, an optimized CAVLC decoder architecture is proposed, which mainly includes level decoding module and RunBefore decoding module. level decoding module uses pseudo-parallel structural decoding amplitude, achieving a half-cycle decoding an amplitude; using RunBefore and level fast combination method, RunBefore decoding completed while forming the residual coefficient. The RTL model of the optimized structure is established and the correctness of its function is verified. The design is integrated using Xilinx ISE13.3 and the results show that the design supports real-time decoding of 1 080p HD video.