论文部分内容阅读
机电部十三所为了向国庆四十周年献礼,于1989年9月25日研制出208门GaAs超高速门阵列芯(母)片,本门阵列利用CAD技术及BFL(缓冲场效应管逻辑)结构,由30个标准单元以及20个输入缓冲级和20个输出缓冲级构成。门阵芯片面积为4070×3630μm~2。采用1μm W-Si难熔栅自对准全离子注入工艺制造。每个标准单元可根据需要联成四个输入或非门;四输入与非门;四输入与或非门等多种电路形式。可完成高电流驱动、低电流驱动、输出电
In order to celebrate the 40th anniversary of the National Day, the Ministry of Electrical and Mechanical Services developed 208 GaAs ultra-high speed gate array chips on September 25, 1989. The gate array uses CAD technology and BFL (Buffer Field Effect Logic) The structure consists of 30 standard cells and 20 input buffers and 20 output buffers. Gate array chip area of 4070 × 3630μm ~ 2. Using 1μm W-Si refractory gate self-aligned all-ion implantation process. Each standard cell can be combined into four input or non-gate; four input NAND gate; four input and NOR gate and other circuit forms. Can be completed high current drive, low current drive, output power