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报道了一种用于制作高速数字及混合模拟/数字LSI/VLSI集成电路的平面离子注入自对准栅技术。采用增强型(e-型)n~+-(Al,Ga)As/MODFET,超晶格MODFET及掺杂沟道异质结构场效应晶体管(DCHFET),实现了4位模-数转换器,2500门8×8乘法器/累加器和4500门16×16复数乘法器,其外延层采用的是分子束外延生长。利用标称栅长1μm的器件,已做出有实际电路结构的直接耦合场效应逻辑(DCFL)环形振荡器,其传播延迟为30ps/级,功耗为1.2mW/级。在LSI电路运用时,若加载一个2.5门的平均扇出并采用大约长1000μm的高密度互连线,则这些门的延迟为89ps/门,功耗为1.38mW/门。室温下,高性能的电压比较器电路在Nyquist模拟输入频率下的取样速率大于2.5GHz,静态滞后小于1mV。已做出工作频率高达2GHz的全函数4位A/D转换电路。据我们所知,这是迄今报道的应用MBE生长LSI异质结构FET技术制作的最大的数字和混合模拟/数字电路。
Reported a planar ion implantation self-aligned gate technology for fabricating high speed digital and mixed analog / digital LSI / VLSI integrated circuits. A 4-bit analog-to-digital converter (ADC) is implemented with enhanced (n-+) AlGaAsAs / MODFETs, superlattice MODFETs and doped channel heterostructure field effect transistors (DCHFETs) 2500 gate 8 × 8 multiplier / accumulator and 4500 16 × 16 complex multipliers, the epitaxial layer using molecular beam epitaxial growth. A direct coupled field effect logic (DCFL) ring oscillator with an actual circuit structure has been fabricated with a device with a nominal gate length of 1 μm, with a propagation delay of 30 ps / level and a power consumption of 1.2 mW / level. When an LSI circuit is loaded, with a 2.5-gate average fan-out and a high density interconnect of approximately 1000μm, these gates have a delay of 89ps / gate and a power consumption of 1.38mW / gate. At room temperature, the high-performance voltage comparator circuit has a sampling rate of> 2.5GHz at the Nyquist analog input frequency and a static hysteresis of less than 1mV. A full-function 4-bit A / D conversion circuit having a working frequency of up to 2 GHz has been made. To the best of our knowledge, this is the largest digital and hybrid analog / digital circuit hitherto reported using MBE grown LSI heterostructure FET technology.