论文部分内容阅读
利用休眠晶体管、多阈值和SEFG技术(源跟随求值门技术),设计了一种新型的p结构多米诺与门.HSPICE仿真结果表明,在相同的时间延迟下,与标准双阈值多米诺与门、标准低阈值多米诺与门和SEFG结构相比,提出的新型多米诺与门的漏电流分别减小了43%,62%和67%,噪声容限分别增大了3.4%,23.6%和13.7%.从而有效地解决了亚65nm工艺下多米诺与门存在的漏电流过大,易受干扰的问题.分析并得到了不同结构的休眠多米诺与门的漏电流最低的输入矢量和时钟状态.
A novel p-structure domino-AND gate is designed by using sleep transistor, multi-threshold and SEFG technique (source-follower evaluation gate technique) .HSPICE simulation results show that with the same time delay, compared with the standard double threshold domino-AND gate, The proposed new domino-to-gate leakage current is reduced by 43%, 62% and 67%, respectively, and the noise margin increases by 3.4%, 23.6% and 13.7%, respectively, compared with the standard low threshold domino gate and SEFG structure. Thus effectively solving the problem that the leakage current in the sub-65nm process is too large and susceptible to interference, and the input vector and clock state with the lowest leakage current of dormant Dominoes and gates with different structures are analyzed and obtained.