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介绍了一种适用于多厂商、多种工艺和电路结构的嵌入式SRAM IP核编译器设计方法,该方法使编译器的设计复杂度降低30%以上。专用版图处理工具LayoutBuilder能自动完成版图拼接、打孔、画线、添加端口和生成GDSII版图文件等。专用网表处理工具NetlistBuilder仅用三个函数即可完成网表的生成,同时,该工具还内嵌自动检查端口数目和对齐方式、自动检查内部浮空节点和自动检查浮空端口等功能。介绍了一种编译器验证流程和时序与功耗文件的生成方法。用这个方法开发了针对2种工艺、3种电路结构的8个编译器。对编译器生成的IP核进行了流片验证。结果表明,该方法可以生成满足不同要求的SRAM IP核。
This paper introduces a design method of embedded SRAM IP core compiler which is suitable for multi-vendor, multi-process and circuit structures. This method reduces the compiler’s design complexity by more than 30%. Special layout processing tools LayoutBuilder can automatically complete layout stitching, drilling, drawing lines, add ports and generate GDSII layout files. NetlistBuilder tool only netlistBuilder only three functions to complete the netlist generation, at the same time, the tool also automatically check the port number and alignment, automatically check the internal floating node and automatically check the floating port and other functions. A compiler verification flow and a method for generating timing and power consumption files are introduced. This method has been developed for two kinds of processes, three kinds of circuit structure of eight compilers. The compiler-generated IP cores were streamed. The results show that this method can generate SRAM IP core to meet different requirements.