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正码速调整设备的作用是把标称速率相同,但瞬时速率不同的m个异步数字流,分别调整到比其自身稍高的同一速率上,使之变成相互同步的m个数字流,以便同步复接。因此对于每个异步支路都要配备一个码速调整设备。一、码速调整原理正码速调整设备主要由N级缓冲存储器及其控制部件构成。其中N级缓冲存储器的写入时钟就是支路时钟f_l,N级缓冲存储器的读出时钟就是同步时钟cl_T。两者保持下述关系:
The function of a positive code speed adjusting device is to adjust m asynchronous digital streams with the same nominal speed but different instantaneous rates to the same rate slightly higher than itself to make them m digital streams synchronized with each other, In order to synchronize multiplexing. Therefore, each asynchronous branch should be equipped with a code speed adjustment equipment. First, the code speed adjustment principle Code speed adjustment device is mainly composed of N-level buffer memory and control components. The write clock of the N-level buffer is the branch clock f_l, and the read clock of the N-level buffer is the synchronous clock cl_T. The two keep the following relationship: