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随着数字技术的不断发展,数字滤波在数字信号处理领域占据不可替代的地位。文章首先介绍了数字滤波器的理论,DSP器件在高速和实时系统中的应用有一定局限性的问题提出了基于FPGA消除基带传输系统码间干扰的实现方案。该方案设计了一个33阶的具有对称转置结构的平方根升余弦滚降(SRRC)滤波器。首先通过MATLAB对滤波器系数进行了提取,并对浮点型系数进行量化和CSD编码形成定点型系数,使之能够在FPGA中运行。利用硬件描述语言Verilog对所设计的滤波器各功能模块进行设计。最后釆用仿真综合软件Modelsim和Quartus Ⅱ对顶层模块进行综合与仿真。仿真后得到的滤波后数据波形图与Matlab下理论性的滤波后数据波形图基本相吻合,证明了所设计的SRRC数字滤波器功能完全正确。
With the continuous development of digital technology, digital filtering occupies an irreplaceable position in the field of digital signal processing. The article first introduces the theory of digital filter, the application of DSP device in high-speed and real-time system has some limitations. The paper proposes a scheme to eliminate intersymbol interference in baseband transmission system based on FPGA. The scheme designs a 33-order square root raised cosine roll-off (SRRC) filter with a symmetric transposed structure. Firstly, the filter coefficients were extracted by MATLAB, and the floating-point coefficients were quantized and CSD-coded to form fixed-point coefficients so that they could run in the FPGA. The hardware design language Verilog is used to design the functional modules of the filter. Finally, using simulation software Synthesis Models Modelsim and Quartus Ⅱ synthesis and simulation of the top-level module. The filtered data waveform obtained after simulation basically matches with the theoretical filtered data waveform under Matlab, which proves that the designed SRRC digital filter function is completely correct.