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ECL母片法门阵列为制作现代计算机主机系统和其它高速数据处理系统要求的多品种特殊逻辑功能集成电路提供了最大的灵活性。 门阵列母片法就是把芯片设计成一个含有标准逻辑门的阵列,用一套固定的掩模完成芯片上的晶体管、二极管、电阻等元件的制作,最后,根据需要,用多层布线互连成不同的逻辑功能组件。业已证明,这种方法在技术上是行得通的,在经济上是合算的。
The ECL mother-of-f method array offers maximum flexibility for the fabrication of a wide range of specialty logic-enabled integrated circuits required by modern computer mainframe systems and other high-speed data processing systems. Gate array chip method is to design the chip into a standard logic gate array, with a fixed mask to complete the chip transistors, diodes, resistors and other components of the production, and finally, as needed, with multi-layer wiring interconnect Into different logical functional components. This method has proved to be technically feasible and cost-effective.