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如今,SoC 设计对片上资源的需求不断增长,而总线结构却不能满足片上通信的要求。因此,设计者开始研究一种新颖的、可扩展的、模块化的设计方法学——片上网络。作者在这个领域中的主要工作是对 H.264 编码器进行通信量建模的仿真,并在规则及专用的 NoC 结构下提出相关的映射方法。首先,使用帧速率和分布拟合方法对H.264 编码器各个模块之间的通信量行为进行了仿真和分析;然后得到了 H.264 编码器专用的重要仿真参数的模型,如带宽、延时、包尺寸等;并利用这些通信量行为模型和参数将 H.264 编码器映射到二维网孔和专用 NoC 结构中;最终使用 Network Simulator-2 比较各参数,如平均包延时,丢包率和面积。另外,还比较了两种 NoC 结构在短期行为中的平均包延时。比较结果显示,专用 NoC 具有更低的平均包延时,更小的丢包率和更少的面积。
Today, SoC designs have a growing need for on-chip resources, and the bus architecture can not meet the requirements of on-chip communications. As a result, designers began to explore a novel, extensible, modular design methodology-on-chip network. The author’s main work in this field is to simulate the H.264 encoder traffic modeling and to propose the relevant mapping methods under the rules and special NoC structure. Firstly, the frame rate and distribution fitting method were used to simulate and analyze the traffic behavior of each module of H.264 encoder. Then the models of important simulation parameters, such as bandwidth, delay Time, packet size, etc .; and use these traffic behavior models and parameters to map the H.264 encoder to two-dimensional cells and a dedicated NoC structure; finally use Network Simulator-2 to compare parameters such as average packet delay, Packet rate and area. In addition, the average packet delay of two NoC structures in short-term behavior is also compared. The comparison shows that the dedicated NoC has a lower average packet delay, a smaller packet loss rate and a smaller area.