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5. The Effects of Plasma Atomic Layer Deposited TiN on MOS device: deposition temperature, capping and

The Effects of Plasma Atomic Layer Deposited TiN on MOS device: deposition temperature, capping and

来源 :2011年第三届微电子及等离子体技术国际会议 | 被引量 : 0次 | 上传用户：cashwang

【摘 要】

：

Recently,3D device structure with high-k gate dielectric/metal gate (HKMG) such as Tri-Gate transistor for 22nm node technology was reported to enhance performance and lower power dissipation.

【作 者】

：

Seung Chan Heo Changhwan Choi 

【机 构】

：

Division of Materials Science and Engineering, Hanyang University, 17 Haengdang-Dong, Seongdong-Gu,S

【出 处】

：

2011年第三届微电子及等离子体技术国际会议

【发表日期】

：

2011年9期

【关键词】

：

Plasma ALD TiN Flatband Voltage 

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Recently,3D device structure with high-k gate dielectric/metal gate (HKMG) such as Tri-Gate transistor for 22nm node technology was reported to enhance performance and lower power dissipation.

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