在数字滤波、离散傅里叶变换等数字信号处理中,乘法运算是一个最基本的运算,乘法运算的速度决定着数字系统的运算速度。本文通过理论与实验研究相结合的方法介绍CSD编码乘法器的运算法则及其在FPGA中的实现过程。通过与二进制乘法器相比较,证明CSD编码乘法器在减少对FPGA资源的占用和提高运算速度方面具有明显的效果。 In digital filtering, discrete Fourier transform and other digital signal processing, multiplication is a basic operation, the speed of multiplication determines the speed of the digital system. In this paper, we introduce the algorithm of CSD code multiplier and its implementation in FPGA through a combination of theoretical and experimental research. Compared with the binary multiplier, it proves that the CSD coding multiplier has a significant effect in reducing the occupation of FPGA resources and increasing the computing speed.