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设计了一款适用于无线通讯系统的3.3V,10位50 MS/s流水线型模数转换器。减小面积和功耗是设计的核心。通过运放共享技术,减小了芯片功耗和面积;使用耗尽型MOS管改进的CMOS开关替代栅压自举开关,节省了开关面积;采用薄栅器件作为主运放的输入管,提高了运放带宽,减小了运放的面积和功耗;采用耗尽型MOS管设计辅助运放,减小了辅助运放的功耗。基于华虹NEC 0.13μm 1P6M CMOS工艺,ADC核心版图面积仅为0.2mm2,功耗为45mW;在50 MHz采样频率,11 MHz输入信号下,SFDR达78dB,SNDR达60.7dB,有效位数为9.8位。
A 3.3V, 10-bit 50 MS / s pipelined analog-to-digital converter is designed for wireless communication systems. Reduce area and power consumption is the core of the design. Through the op amp sharing technology to reduce the chip power consumption and area; the use of depleted MOS transistor CMOS switch instead of gate voltage bootstrap switch, saving the switch area; the use of thin gate devices as the main op amp input pipe to improve The op amp bandwidth, reducing the op amp area and power consumption; depletion mode MOS tube design to help op amp, reducing the power consumption of the auxiliary op amp. Based on Hua Hong NEC 0.13μm 1P6M CMOS process, the ADC core layout has an area of only 0.2mm2 and a power consumption of 45mW. At a sampling frequency of 50MHz, an SFDR of 78dB, an SNDR of 60.7dB and an effective number of bits of 9.8MHz at an input signal of 11MHz Bit.