在带电荷泵的锁相环频率综合器中,设计低杂散锁相环的关键是减少鉴频鉴相器和电荷泵的非理想特性以及提高压控振荡器的性能。采用TSMC 0.18μm CMOS工艺,设计了一种改进型锁相环电路。仿真结果显示,在1.8V基准电压供电时,电荷泵电流在0.3～1.6V电压范围内匹配度小于1μA,电流失配率小于0.2%,压控振荡器在中心频率2.4GHz频偏1MHz时的相位噪声为-124.3dBc/Hz@1MHz,环路参考杂散降为-60dBm。 In charge-pump PLL frequency synthesizers, the key to designing a low-spurious PLL is to reduce the non-ideal behavior of the phase-frequency detector and charge pump, and improve the performance of the VCO. Using TSMC 0.18μm CMOS technology, an improved PLL circuit is designed. Simulation results show that the matching degree of the charge pump current is less than 1μA in the voltage range of 0.3 ~ 1.6V, the current mismatch rate is less than 0.2% when the 1.8V reference voltage is supplied, and the VCO frequency is 1MHz when the center frequency is 2.4GHz The phase noise is -124.3dBc / Hz@1MHz, and the loop reference spurs drop to -60dBm.