在CMOS数字IC中的数据锁存器需要双相时钟信号(OUT和OUT),并要求这两相信号的同时跳变不受输出负载的影响。例如,在图(a)所示的基本电路输出存在一个门延时的时间间隔,这种电路增加时间与负载的斜度会引起虚假的锁存。在电路中加入第三个反相门(图b),可消除随负载变化的时间斜度,但这样的电路也 Data latches in CMOS digital ICs require two-phase clock signals (OUT and OUT) and require that the simultaneous transitions of the two-phase signals be unaffected by the output load. For example, there is a gate delay between the output of the basic circuit shown in Figure (a), and the ramp-up of this circuit with respect to load can cause false latching. Adding a third inverting gate to the circuit (Figure b) eliminates the time-dependent slope of the load, but such a circuit also