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集成电路的快速发展,迫切地需要快速、高效、低成本且具有可重复性的测试方案,这也成为可测性设计的发展方向。此次设计基于一款电力线通信芯片,数字部分采用传统常用的数字模块扫描链测试和存储器内建自测试;同时利用芯片正常的通信信道,引入模拟环路测试和芯片环路内建自测试,即覆盖了所有模拟模块又保证了芯片的基本通信功能,而且最大限度地减少了对芯片整体功能布局的影响。最终使芯片良率在98%以上,达到了大规模生产的要求。此设计可以为当前数模混合通信芯片的测试提供参考。
The rapid development of integrated circuits urgently needs fast, efficient, low-cost and repeatable test solutions, which have also become the development direction of testability design. The design is based on a power line communication chip. The digital part adopts the commonly used digital module scan chain test and the built-in self-test of the memory. Meanwhile, the normal communication channel of the chip is used to introduce the analog loop test and the built-in self-test of the chip loop, That covers all the analog modules and ensure the basic communication functions of the chip, but also to minimize the overall functional layout of the chip. Ultimately the chip yield above 98%, reaching the requirements of mass production. This design can provide a reference for the current digital-analog hybrid communication chip test.