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Abstract：In recent years, as China has finished the updating of the fourth generation of network, for guaranteeing the information security of the state, communication chip with complete independent intellectual property right must be possessed to support the advancement of such project. TD-LTE Baseband Chip is a super-large-scale integrated circuit designed basing on SOC, which needs to carry out coding, etc to the transmitted baseband signal, or carry out decoding, etc to the received baseband signal. LPDDR2 SDRAM is used in the chip design process due to its low power dissipation, high capacity and high reliability. As PHY in the controller architecture of LPDDR2 SDRAM adopts hard core design, it cannot be achieved in Virtex-7 2000T prototype verification platform. This design mainly builds on such prototype verification platform to propose the verification scheme of LPDDR2 SDRAM controller in TD_LTE baseband chip, so as to guarantee that prototype verification in FPGA can be carried out by TD_LTE baseband system, and meanwhile high capacity storage space can be provided to the system.
Key words：LPDDR2 SDRAM;Chip Verification;TD-LTE Baseband Chip;Prototype Verification
1 Introduction
With the completion of fourth-generation network update in China, there must be the communication chip with completely independent intellectual property right to promote the project, so that the national information security will be safe. Based on the SOC design, TD-LTE baseband chip performs a coding process on baseband signal to be transmitted or performs a decoding process on baseband signal received. Specially, compile the audio signal to baseband code to be transmitted when sending while interpret the baseband code received into audio signal when receiving. Meanwhile, it also performs a coding process on address information like telephone numbers and websites and texts of SMS and websites. Thus, TD-LTE baseband chip is the essential component in the establishment of fourth-generation network.
This paper introduces SOC architecture design of TD-LTE baseband chip and validates the whole scheme based on FPGA prototype. Besides, it focuses on LPDDR2 SDRAM authentication scheme based on verification process of FPGA prototype depending on reliability and stability and analyze the implantation and result of the scheme during the process. It turns out that the design could meet the performance index of system.
2 System Architecture of TD-LTE Baseband Chip 2.1 Overall Architecture of Chip
Based on the VLSI of SOC design, TD-LTE baseband chip performs a coding process on baseband signal to be transmitted or performs a decoding process on baseband signal received. Mainly includes the following parts:
The OpenRisc1200 processor: the RISC (Reduced Instruction Set Computer) processor with open source code based on GPL protocol uses the architecture of free open 32/64bit RISC/DSP. The processor completes the transport-level description of RISC/DSP architecture register through description of Verilog HDL language by hardware. With mature technology and good performance, it is generalized that the performance of it is between ARM7 to ARM8 which is applicable to embedded devices. Attaching with the powerful chain-tool such as tool for software development, CPU simulation model, operating system and function library of software application, it also has the perfect standardized protocol interface to speed up the integrated efficiency.
Direct Memory Access: Realize the communication between hardware devices in various speeds with no relying on large amount pf interrupting loading of CPU. It can copy the data from a section of address space to another section of address space. In the baseband chip, DMA moves mobile external memory data to faster memory region of the chip. In the system, it can speed up mobile efficiency of data.
Shared memory: Large capacity storage unit can be visited by several processors when there are several processors in the system.
The system of chip also includes DSP data processing module, radio frequency transmission and receiving module, uplink and downlink processing module, Clock generating control module and universal interface module. Show as follow.
2.2 Architecture in the system of LPDDR2
In the chip system, LPDDR SDRAM module connect to the system with 64 bit AXI bus among which the ddr2_ctr_subsystem of LPDDR2 system contains AXI conversion module, AXI protocol to AHB protocol module and AHB module while the cadenc_mc_asic contains control module of LPDDR SDRAM and physical layer switching module. And mobile_ddr2 is the storage particle simulation model of LPDDR2 SDRAM. It can simulate the real running of LPDDR2 SDRAM control system.
3 Architecture of LPDDR2 and Verified Design
D-LTE baseband chip system need FPGA prototype verification on the verification platform, but PHY of LPDDR2 SDRAM control system is hard-core which cannot be verified on the FPGA platform and there are available so-dimm slot based on DDR2on the development board. So replace DDR2 control system with LPDDR2 system to provide large capacity storage space for the system. 3.1 Design of DDR2 SDRAM Controller
There is the need to design DDR2 SDRAM controller with the same data bit, address bit and BANK quantity of LPDDR2 SDRAM to provide storage space of the system to make sure that AXI interface of DDR2 SDRAM controller and AXI interface of LPDDR2 SDRAM controller matches. Structure of control system, see in picture 3.
The Infrastructure module uses to generate and distribute clock of all the modules in control system. Besides, all the reset signals are controlled by DCM.
There is the phase locked loop internal. With the reference signal of external input, control the frequency and phase of oscillator signal in internal loop. The PLL could provide accurate comprehensive clock, reduce shake and realize the function of filter. The module also includes Delay calibration module which calibrates the delay of DQS to DQ, guarantee the center position of DQS in DQ valid window to lock and store DQ.
In Iodelay_ctrl module, the IDELAYCTRL elements of Virtex-7 FPGA have been instantiated. IDELAYCTRL element calibrates the delay in its range continuously to reduce the impact of design leading from deviation of temperature and voltage. There is the need of 200MHz clock input in its regular work.
clk_ibuf module initializs the input of clock buffer to keep the good characteristics of the clock. memc_ui_top_axi module is the main part of the verification. It contains two parts which are controlle (with AXI4 interface) module and PHY module. Explain them respectively as follows:
Controlle (with AXI4 interface) module is the main controller of Virtex-7 DDR2 SDRAM controller reference design. It generates all the control signals for DDR2 storage interface and user interface. All the command and control signals are generated based on input burst length and CAS delay.
PHY module is the physical layer module for the verification. Physicallayer contains IOBs and some elements used for reading and writing the double data rate signal in the memory such as IDDR2 and ODDR2. The module also includes IODELAY element of Virtex-7FPGA. Combine the module with DDR2 IP core control of ES05.
3.2 Establishment and Simulation of DDR2 SDRAM Simulation Model System
3.2.1 Establishment of Simulation Model System
After the completion of above DDR2 controller, there is the need to verify whether DDR2 SDRAM controller can be used accurately with simulation of the model. The testing system mainly contains three parts which are testing excitation, DDR2 SDRAM controller and DDR2 SDRAM simulation model. 3.2.1.1 Testing Excitation
Testing excitation module mainly includes Traffic Generator module and AXI Wapper module. Traffic Generator module is the system testing program. The module stores information into corresponding FIFO which are user’s data, demand and address information generating from lfsr. When writing operation, the data of FIFOs is read out and sent to physical layer to store in memory. When reading operation, data in memory is read out and wrote in FIFOs. AXI Wapper module is a module for reading and writing transmission conversion of data by AXI4 protocol. With the module, signal, address, controlling information and data does AXI4 protocol transmission.
3.2.1.2 DDR2 Simulation Model
The DDR2 SDRAM simulation model is mainly used in the replacement of the real DDR2 SDRAM. During the simulation, the written data can be read out to compare to verify whether the design of DDR2 SDRAM controller is accurate.
3.2.2 Simulation and Result Analysis
Use VCS-verilog compiled simulator of SYNOPSYS Company to simulate with the advantage of fast speed of simulation and multiple call methods.
Start the signal of clock and remain stable of the signal, then drive CKE up. After a moment, issue demand of precharge to clusters and cancel the demand after another moment. Initialize the system, drive up CKE. With the execution of the precharge demand, execute external model register load instruction after 1950ns and configure EMR with initialization of EMR1 and EMR2. Execute the model register load instruction and configure memory parameter such as BL, ODT configuration and CAS delay. Execute PCH instruction and reprecharge all the bank.. Execute the ARF instruction for twice. Execute LMR instruction and set operation parameter. Execute ELMR instruction and set impedance of OCD as windows default by EMR.
init_calib_complete=1 refers to the completion of DDR2 initialization as picture 5 shows and the normal read and write operations can be done. Picture 6 and picture 7 refers to the read and write operation with 16’h1118 as the initial address and 8 as BL. The reading data and writing data of the same address are similar which means DDR2 SDRAM control system can do regular work.
4 Integration and Implementation of System
After simulating with VCS software, the following summarizes the integration of system with synplify_premie software and implementation of system with vivado software to guarantee the regular work on the verification platform. 4.1 Process Description
4.1.1 Integration
Integration refers to the simple device description of transformation from higher-level description logic to lower-level description logic. In general, integration is based on RTL code. That is to say, convert the transmission-level model, algorithm, behavior and function description of memory into corresponding netlist file of FPGA/CPLD basic structure which means compiling design input to logical connective including basic logic units of and, or, non, ram and memory.
4.1.2 Implementation and wiring
The implementation could only wiring on the integration network table. Configure the integration network table to specific FPGA development platform and select the optimal speed and area. Connect each component correctly and reasonably with connection resources and logic resources of internal chip to implement corresponding logic function.
4.1.3 Programming and Debugging of Chip
Generate data stream and download to FPGA verification platform to debug with third-party tools. The embedded online logic analysis is the major debugging aid. It can grasp large number of real-time signals with occupation of little logic resources to determine whether the system works regularly.
4.2 Integration, Implementation and Platform Debugging
The integration tool is synplify_premier with the advantage of turning the module that cannot be integrated such as divider module into network table which are available on FPGA platform in ASIC design, and then integrate the network table to provide convenience for integration system. Analysis report on the share of DDR2 SDRAM control system in resources after integration shows as follow.
Register bits not including I/Os:14578
Latch bits not including I/Os:14
RAM/ROM usage summary
Simple Dual Port Rams (RAM32M):141
Global Clock Buffers:2 of 32
Mapping Summary:
Total LUTs:9197
Distribution of All Consumed LUTs=SRL+RAM+ LUT+ LUT2+LUT3+LUT4+LUT5+LUT6+LUT6_2-HLUTNM/2
Distribution of All Consumed Luts 9197=655+564+ 423+1104+1268+1089+1523+4019+21-2938/2
Number of unique control sets:300
From the analysis table, we can find that 9197 LUT resources have been used in system circuit while the number of dual-port RAM used is 141. Through the resource quantity of each part, we can conclude the unreasonable use of resource. so that we can optimize them with different emphases to reduce the use of resource and save the logic resources in platform developing. Because the timing analysis report is too much and too long, here is only small part of it shows as follow. Among which, slack=0.139ns refers to the delay of clock period constraint is 0.139ns more than real delay after the wiring. The system works regularly if the constraint conditions are met.
When the implementation is done, there is the need of vivado software to translate the integrated network table into the bottom module and hardware primitive of the selected device and reflect the design to the structure of device to wiring. So that, we can implement the design circuit on Virex-7 2000T chip generated from Xilinx. After implementation, the circuit effect and the share in logic resources on the chip show in the following picture.
After integration and implementation, circuit generates this picture. There are no red connecting lines in the picture which means there are no circuits and devices that have not be wiringed. It refers to that the integration and implementation has done and can enter the process of generating bit file.
Debug the Verification Platform of DDR2 SDRAM Controller
The debugging platform, taking Virtex-7 2000T FPGA, XC7V2000TFLG1925 of Xilinx Company as the core, supports design verification of more than 40million logic gate. With So-dimm slot based on DDR2, it can meet the debugging condition. The software integrates with synplify_premier, configures high-speed clock and downloads files with TAI software of S2C company and capture real-time waveform with Debug software in vivado2012.04 to debug.
Testing structure removes modules that cannot integrate and implement based on simulation model and DDR2 SDRAM controller simulation model to restrict pins. At that time, put pin to high-speed clock logic resource block correspondingly, or it can not do regular work. Integrate and wiring the whole system and then generate the .bit and .ltx file that can be downloaded and debugged with attention that there should be corresponding debugging model added before. Replace DDR2 module that cannot be integrated in the simulation system with DDR2 memory chip of simulation model.
4.3 simulation and result analysis
Download with DEBUG of vivado14.4 version software and debug and analyze with FPGA verification platform, and then get the real-time signal graph of AXI interface, shows as follow.
To verify better, set BL to something that can be generated from FLSR. From the picture, we can find that writing 76 digits and 198 digits when BL is 76 or 198, the digits read out is the same. That means the signal of the verification system is of completeness, the affect that electromagnetic interference have on regular work is acceptable and DDR2 SDRAM controller can do regular work and can be integrated to baseban chip system.
Key words：LPDDR2 SDRAM;Chip Verification;TD-LTE Baseband Chip;Prototype Verification
1 Introduction
With the completion of fourth-generation network update in China, there must be the communication chip with completely independent intellectual property right to promote the project, so that the national information security will be safe. Based on the SOC design, TD-LTE baseband chip performs a coding process on baseband signal to be transmitted or performs a decoding process on baseband signal received. Specially, compile the audio signal to baseband code to be transmitted when sending while interpret the baseband code received into audio signal when receiving. Meanwhile, it also performs a coding process on address information like telephone numbers and websites and texts of SMS and websites. Thus, TD-LTE baseband chip is the essential component in the establishment of fourth-generation network.
This paper introduces SOC architecture design of TD-LTE baseband chip and validates the whole scheme based on FPGA prototype. Besides, it focuses on LPDDR2 SDRAM authentication scheme based on verification process of FPGA prototype depending on reliability and stability and analyze the implantation and result of the scheme during the process. It turns out that the design could meet the performance index of system.
2 System Architecture of TD-LTE Baseband Chip 2.1 Overall Architecture of Chip
Based on the VLSI of SOC design, TD-LTE baseband chip performs a coding process on baseband signal to be transmitted or performs a decoding process on baseband signal received. Mainly includes the following parts:
The OpenRisc1200 processor: the RISC (Reduced Instruction Set Computer) processor with open source code based on GPL protocol uses the architecture of free open 32/64bit RISC/DSP. The processor completes the transport-level description of RISC/DSP architecture register through description of Verilog HDL language by hardware. With mature technology and good performance, it is generalized that the performance of it is between ARM7 to ARM8 which is applicable to embedded devices. Attaching with the powerful chain-tool such as tool for software development, CPU simulation model, operating system and function library of software application, it also has the perfect standardized protocol interface to speed up the integrated efficiency.
Direct Memory Access: Realize the communication between hardware devices in various speeds with no relying on large amount pf interrupting loading of CPU. It can copy the data from a section of address space to another section of address space. In the baseband chip, DMA moves mobile external memory data to faster memory region of the chip. In the system, it can speed up mobile efficiency of data.
Shared memory: Large capacity storage unit can be visited by several processors when there are several processors in the system.
The system of chip also includes DSP data processing module, radio frequency transmission and receiving module, uplink and downlink processing module, Clock generating control module and universal interface module. Show as follow.
2.2 Architecture in the system of LPDDR2
In the chip system, LPDDR SDRAM module connect to the system with 64 bit AXI bus among which the ddr2_ctr_subsystem of LPDDR2 system contains AXI conversion module, AXI protocol to AHB protocol module and AHB module while the cadenc_mc_asic contains control module of LPDDR SDRAM and physical layer switching module. And mobile_ddr2 is the storage particle simulation model of LPDDR2 SDRAM. It can simulate the real running of LPDDR2 SDRAM control system.
3 Architecture of LPDDR2 and Verified Design
D-LTE baseband chip system need FPGA prototype verification on the verification platform, but PHY of LPDDR2 SDRAM control system is hard-core which cannot be verified on the FPGA platform and there are available so-dimm slot based on DDR2on the development board. So replace DDR2 control system with LPDDR2 system to provide large capacity storage space for the system. 3.1 Design of DDR2 SDRAM Controller
There is the need to design DDR2 SDRAM controller with the same data bit, address bit and BANK quantity of LPDDR2 SDRAM to provide storage space of the system to make sure that AXI interface of DDR2 SDRAM controller and AXI interface of LPDDR2 SDRAM controller matches. Structure of control system, see in picture 3.
The Infrastructure module uses to generate and distribute clock of all the modules in control system. Besides, all the reset signals are controlled by DCM.
There is the phase locked loop internal. With the reference signal of external input, control the frequency and phase of oscillator signal in internal loop. The PLL could provide accurate comprehensive clock, reduce shake and realize the function of filter. The module also includes Delay calibration module which calibrates the delay of DQS to DQ, guarantee the center position of DQS in DQ valid window to lock and store DQ.
In Iodelay_ctrl module, the IDELAYCTRL elements of Virtex-7 FPGA have been instantiated. IDELAYCTRL element calibrates the delay in its range continuously to reduce the impact of design leading from deviation of temperature and voltage. There is the need of 200MHz clock input in its regular work.
clk_ibuf module initializs the input of clock buffer to keep the good characteristics of the clock. memc_ui_top_axi module is the main part of the verification. It contains two parts which are controlle (with AXI4 interface) module and PHY module. Explain them respectively as follows:
Controlle (with AXI4 interface) module is the main controller of Virtex-7 DDR2 SDRAM controller reference design. It generates all the control signals for DDR2 storage interface and user interface. All the command and control signals are generated based on input burst length and CAS delay.
PHY module is the physical layer module for the verification. Physicallayer contains IOBs and some elements used for reading and writing the double data rate signal in the memory such as IDDR2 and ODDR2. The module also includes IODELAY element of Virtex-7FPGA. Combine the module with DDR2 IP core control of ES05.
3.2 Establishment and Simulation of DDR2 SDRAM Simulation Model System
3.2.1 Establishment of Simulation Model System
After the completion of above DDR2 controller, there is the need to verify whether DDR2 SDRAM controller can be used accurately with simulation of the model. The testing system mainly contains three parts which are testing excitation, DDR2 SDRAM controller and DDR2 SDRAM simulation model. 3.2.1.1 Testing Excitation
Testing excitation module mainly includes Traffic Generator module and AXI Wapper module. Traffic Generator module is the system testing program. The module stores information into corresponding FIFO which are user’s data, demand and address information generating from lfsr. When writing operation, the data of FIFOs is read out and sent to physical layer to store in memory. When reading operation, data in memory is read out and wrote in FIFOs. AXI Wapper module is a module for reading and writing transmission conversion of data by AXI4 protocol. With the module, signal, address, controlling information and data does AXI4 protocol transmission.
3.2.1.2 DDR2 Simulation Model
The DDR2 SDRAM simulation model is mainly used in the replacement of the real DDR2 SDRAM. During the simulation, the written data can be read out to compare to verify whether the design of DDR2 SDRAM controller is accurate.
3.2.2 Simulation and Result Analysis
Use VCS-verilog compiled simulator of SYNOPSYS Company to simulate with the advantage of fast speed of simulation and multiple call methods.
Start the signal of clock and remain stable of the signal, then drive CKE up. After a moment, issue demand of precharge to clusters and cancel the demand after another moment. Initialize the system, drive up CKE. With the execution of the precharge demand, execute external model register load instruction after 1950ns and configure EMR with initialization of EMR1 and EMR2. Execute the model register load instruction and configure memory parameter such as BL, ODT configuration and CAS delay. Execute PCH instruction and reprecharge all the bank.. Execute the ARF instruction for twice. Execute LMR instruction and set operation parameter. Execute ELMR instruction and set impedance of OCD as windows default by EMR.
init_calib_complete=1 refers to the completion of DDR2 initialization as picture 5 shows and the normal read and write operations can be done. Picture 6 and picture 7 refers to the read and write operation with 16’h1118 as the initial address and 8 as BL. The reading data and writing data of the same address are similar which means DDR2 SDRAM control system can do regular work.
4 Integration and Implementation of System
After simulating with VCS software, the following summarizes the integration of system with synplify_premie software and implementation of system with vivado software to guarantee the regular work on the verification platform. 4.1 Process Description
4.1.1 Integration
Integration refers to the simple device description of transformation from higher-level description logic to lower-level description logic. In general, integration is based on RTL code. That is to say, convert the transmission-level model, algorithm, behavior and function description of memory into corresponding netlist file of FPGA/CPLD basic structure which means compiling design input to logical connective including basic logic units of and, or, non, ram and memory.
4.1.2 Implementation and wiring
The implementation could only wiring on the integration network table. Configure the integration network table to specific FPGA development platform and select the optimal speed and area. Connect each component correctly and reasonably with connection resources and logic resources of internal chip to implement corresponding logic function.
4.1.3 Programming and Debugging of Chip
Generate data stream and download to FPGA verification platform to debug with third-party tools. The embedded online logic analysis is the major debugging aid. It can grasp large number of real-time signals with occupation of little logic resources to determine whether the system works regularly.
4.2 Integration, Implementation and Platform Debugging
The integration tool is synplify_premier with the advantage of turning the module that cannot be integrated such as divider module into network table which are available on FPGA platform in ASIC design, and then integrate the network table to provide convenience for integration system. Analysis report on the share of DDR2 SDRAM control system in resources after integration shows as follow.
Register bits not including I/Os:14578
Latch bits not including I/Os:14
RAM/ROM usage summary
Simple Dual Port Rams (RAM32M):141
Global Clock Buffers:2 of 32
Mapping Summary:
Total LUTs:9197
Distribution of All Consumed LUTs=SRL+RAM+ LUT+ LUT2+LUT3+LUT4+LUT5+LUT6+LUT6_2-HLUTNM/2
Distribution of All Consumed Luts 9197=655+564+ 423+1104+1268+1089+1523+4019+21-2938/2
Number of unique control sets:300
From the analysis table, we can find that 9197 LUT resources have been used in system circuit while the number of dual-port RAM used is 141. Through the resource quantity of each part, we can conclude the unreasonable use of resource. so that we can optimize them with different emphases to reduce the use of resource and save the logic resources in platform developing. Because the timing analysis report is too much and too long, here is only small part of it shows as follow. Among which, slack=0.139ns refers to the delay of clock period constraint is 0.139ns more than real delay after the wiring. The system works regularly if the constraint conditions are met.
When the implementation is done, there is the need of vivado software to translate the integrated network table into the bottom module and hardware primitive of the selected device and reflect the design to the structure of device to wiring. So that, we can implement the design circuit on Virex-7 2000T chip generated from Xilinx. After implementation, the circuit effect and the share in logic resources on the chip show in the following picture.
After integration and implementation, circuit generates this picture. There are no red connecting lines in the picture which means there are no circuits and devices that have not be wiringed. It refers to that the integration and implementation has done and can enter the process of generating bit file.
Debug the Verification Platform of DDR2 SDRAM Controller
The debugging platform, taking Virtex-7 2000T FPGA, XC7V2000TFLG1925 of Xilinx Company as the core, supports design verification of more than 40million logic gate. With So-dimm slot based on DDR2, it can meet the debugging condition. The software integrates with synplify_premier, configures high-speed clock and downloads files with TAI software of S2C company and capture real-time waveform with Debug software in vivado2012.04 to debug.
Testing structure removes modules that cannot integrate and implement based on simulation model and DDR2 SDRAM controller simulation model to restrict pins. At that time, put pin to high-speed clock logic resource block correspondingly, or it can not do regular work. Integrate and wiring the whole system and then generate the .bit and .ltx file that can be downloaded and debugged with attention that there should be corresponding debugging model added before. Replace DDR2 module that cannot be integrated in the simulation system with DDR2 memory chip of simulation model.
4.3 simulation and result analysis
Download with DEBUG of vivado14.4 version software and debug and analyze with FPGA verification platform, and then get the real-time signal graph of AXI interface, shows as follow.
To verify better, set BL to something that can be generated from FLSR. From the picture, we can find that writing 76 digits and 198 digits when BL is 76 or 198, the digits read out is the same. That means the signal of the verification system is of completeness, the affect that electromagnetic interference have on regular work is acceptable and DDR2 SDRAM controller can do regular work and can be integrated to baseban chip system.