论文部分内容阅读
介绍了寄存器堆队列装置（ＦＩＦＯ）的作用和设计原理。传统寄存器队列的设计多采用串行输入一串行输出，或者并行输入－并行输出的方式，该文介绍了两种并行输入－并行输出而且可以“边进边出”的寄存器队列装置，该装置可用于总线接口和先行控制处理机的设计中。
This paper introduces the function and design principle of Register Heap Queue (FIFO). Conventional register queues are designed using a serial input, a serial output, or a parallel input-parallel output. This article describes two types of register-array devices that are parallel-in-parallel and can be “edge-in and edge-out” Can be used in the bus interface and control processor design.