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提出了一种使流水线模数转换器功耗最优的系统划分方法。采用Matlab进行模拟,以信噪比(SNR)为约束,得出一定精度条件下,流水线ADC各子级分辨率和各级采样电容缩减因子的不同选取组合;又以功耗为约束,从以上多种组合中找到满足最低功耗的流水线ADC结构划分方法。基于以上分析,在SMIC 0.35μm工艺条件下,设计了一个10 bit、采样率20 MS/s的流水线ADC,并流片验证。2.1 MHz输入频率下测试,SFDR=73 dB、ENOB=9.18 bit,模拟部分核心功耗102.3 mW。
A system partitioning method is proposed to optimize the power consumption of the pipeline A / D converter. Matlab was used to simulate the signal to noise ratio (SNR) as a constraint to get a certain accuracy, the pipeline ADC resolution of sub-levels and the sampling capacitor reduction factor at different levels of the different selection combinations; and power consumption constraints, from the above A variety of combinations to find the lowest power consumption of the pipeline ADC structure division method. Based on the above analysis, a 10 bit ADC with a sampling rate of 20 MS / s was designed and verified by flow sheeting at a 0.35μm SMIC process. 2.1 MHz input frequency test, SFDR = 73 dB, ENOB = 9.18 bit, analog part core power consumption 102.3 mW.