简要介绍了半并行结构的A/D转换器原理。针对该结构的A/D转换器,提出了一种能自动校零、迟滞、全差分输入及多级前置放大的比较器。解决了输入失调电压、噪声环境下单转换、电荷注入、带宽、转换速度等问题。给出了应用该比较器的0.6μm CMOS半并行A/D转换器的性能。结果表明,设计的比较器能使丰并行ADC的DNL和INL小于±0.5 LSB,SNR大于48dB。 A brief introduction to the semi-parallel structure of the A / D converter principle. A / D converter for the structure, the proposed automatic zero, hysteresis, fully differential input and multi-stage preamplifier. Solve the input offset voltage, single conversion under noisy environment, charge injection, bandwidth, conversion speed and other issues. The performance of a 0.6μm CMOS semi-parallel A / D converter using this comparator is given. The results show that the designed comparator can make DNL and INL less than ± 0.5 LSB and SNR larger than 48 dB for HSBC ADC.