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本文介绍我在研制3J1 RISC机芯片时所设计的指令集模拟器,这个模拟器能模拟和检验指令集设计的合理性及RISC机体系结构与其指令集的合理性和协调性,并能进一步方便地扩展至寄存器级模拟,也可再下到混合级模拟。在针对RISC机研制模拟器时须体现RISC特性,与CISC是有所不同的。本文试图就研。制过程中的某些问题给出处理方式和方法。最后还将说明,3J1 RISC机指令模拟器虽是在3J—RISC机研制过程中产生的,但不仅适于此机。
This article introduces the instruction set simulator I designed when developing the 3J1 RISC chip. This simulator simulates and verifies the rationality of instruction set design and the rationality and coordination of RISC architecture and its instruction set, and further convenience Extended to register-level simulation, but also to the next mixed-level simulation. In the development of simulators for RISC machine must reflect RISC characteristics, and CISC are different. This article attempts to research. Some problems in the process of manufacturing are given ways and means of treatment. Finally, will also show that 3J1 RISC machine instruction simulator is generated in the 3J-RISC machine development process, but not only for this machine.