论文部分内容阅读
在n型单晶硅衬底上,用射频磁控溅射法沉积Si1-xGex薄膜,在850℃下对薄膜进行40min磷扩散,制备出n-poly-Si1-xGex。俄歇电子谱(AES)测试表明,Si1-xGex薄膜的Ge含量约为18%,即磷扩散后得到n-poly-Si0.82Ge0.18。随即在n-poly-Si0.82Ge0.18薄膜上溅射一层Co膜,形成Co/n-poly-Si0.82Ge0.18肖特基结。在90K～332K温度范围内,对样品进行变温I-V测试(I-V-T)。发现随测试温度的升高,表观理想因子na变小,肖特基势垒高度(SBH)变大。这是金属/半导体肖特基接触不均匀性的表现,对这种不均性进行建模,并和实验数据进行对比,两者基本符合。
The n-poly-Si1-xGex thin films were deposited on the n-type monocrystalline silicon substrate by RF magnetron sputtering at 40 ℃ for 40min at 850 ℃. Auger electron spectroscopy (AES) test showed that the Ge content of the Si1-xGex thin film was about 18%, that is, n-poly-Si0.82Ge0.18 was obtained after the phosphorus was diffused. Then a layer of Co film was sputtered on the n-poly-Si0.82Ge0.18 film to form a Co / n-poly-Si0.82Ge0.18 Schottky junction. The samples were subjected to variable temperature I-V test (I-V-T) over the temperature range of 90K to 332K. It is found that as the test temperature increases, the apparent ideality factor na becomes smaller and the Schottky barrier height (SBH) becomes larger. This is a manifestation of the metal / semiconductor Schottky contact inhomogeneity. The modeling of this inhomogeneity is contrasted with the experimental data and the two are basically in line.